FPGA Data Transfer demo #2

This post describes how to set up a project in Xilinx Vivado for writing and configuring the program for FPGA. If you are already familiar with Vivado you can skip this one.

Starting a new project

  1. Open Vivado and select “Create project”.
  2. Select “RTL Project” as a project type and check “Do not specify sources at this time” – they will be added later.
  3. Select the target FPGA model  (for XEM7310-A75 its xc7a75tfgg484-1)
  4. Click Finish

Importing design files

Adding VHDL source files

These files describe each module’s logic and connections between them. Apart from .vhd files, some .xci files are also included in the sources directory. They will be used by Xilinx tool to recreate IP Cores that have been generated by Xilinx Core Generator (that includes FIFOs and DDR3 memory controller). To import the sources:

  • Click “Add sources” -> “Add or create design sources”.
  • Select “Add Directories” and choose the fpga_data_transfer_demo/vhdl_src folder from our repository. Remember to check “Add sources from subdirectories” and “Copy sources into the project” (in case you do not want to modify the original sources). Select the target language as VHDL.
  • Add your FrontPanelHDL files for the XEM7310-A75 board following the same scheme.

Adding constrains file

These files contain the definitions and restrictions for FPGA physical ports in use, including clock ports, DDR3 memory connections, USB signals and LEDs.

  • Click “Add sources” -> “Add or create constrains”
  • Select “Add files” and choose “demo_top.xdc” file located in fpga_data_transfer_demo/vhdl_src/constrs_1 .

Set the demo_top.vhd as a Top module by clicking the right mouse button on the file and selecting “Set as Top”.

After that the Sources tab should look similar to this:

Sources tab in Vivado after importing the files

If you do not see the imported sources, try clicking the right mouse button anywhere on the Sources tab and select “Refresh Hierarchy”.


Finally, Synthesis can be started. The first run will take longer than usual because of the IP Cores that need to be regenerated. If all files were imported correctly the Synthesis should end successfully.

The popup window will appear asking to start implementation but before that, we recommend taking a look at the next post in which the structure of our FPGA application will be introduced.